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Universal LCD/TFT Display Controller Is Fully Configurable

Blaze Display Technology Co., Ltd. | Updated: Nov 24, 2016

Digital Core Design's newest IP Core, the DBLCD32, is a fully configurable, universal LCD/TFT display controller supporting a wide range of resolutions.

 

The core enables both, horizontal and vertical parameters’ synchronization setup. The display’s pixel clock can be generated by an internal pixel clock divider based on the bus clock, or delivered to the core by a dedicated pin. Additionally, an engineer can use an externally generated pixel clock. Its polarization, as well as synchronization signals, are fully configurable.

The DBLCD32 has been also equipped with a DMA capable master interface, which can be used to access a framebuffer, when placed directly in a system memory. Embedded DMA controller has a configurable FIFO to store pixels data, which increases system throughput and performance. The transmission on the master interface is burst oriented and there is a possibility of defining the burst size limit.

Data fetched by the DMA interface can be translated to 24-bits RGB signals, depending on the selected color mode. There are three standard color modes supported: 24-bits True Color, 16-bits (5-6-5) High Color and 8-bits index color mode. Additionally, a 32-bit True Color is also supported, but the MSB byte of each four byte word is ignored. In case of the Indexed Color Mode, the DBLCD32 is equipped with pixel palette RAM, which is used to translate each byte from the display buffer into 24-bit RGB output. There are two different formats of color palettes available. The core supports the page flipping mechanism, which enables the usage of multiple buffering without the tearing effect. The DBLCD32 incorporates also a set of programmable interrupts available related to both display synchronization and DMA status signals. The core can work on both little and big endian systems. To increase the system performance and flexibility of usage, the DLBLCD32 can be configured in two possible optimization levels, to find a proper balance between a gate count and a critical path length.

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